What chipsets are used in HDMI to MIPI DSI adapters?
Core Chipset Architectures and Their Trade-offs
The TC358870XBG, manufactured by Toshiba (now Kioxia), is a dedicated bridge IC that integrates HDMI 1.4b receiver and MIPI DSI transmitter. It supports HDMI input up to 4K at 30Hz (3840x2160) and MIPI DSI output with 1 to 4 data lanes, each running at up to 1 Gbps. The chip handles HDCP 1.4 decryption, EDID emulation (using internal 128-byte EEPROM), and audio extraction for I2S or SPDIF output. Its power consumption is around 300 mW to 500 mW depending on resolution, which is lower than FPGA solutions. The chip’s internal PLL (Phase-Locked Loop) regenerates the MIPI clock from the HDMI TMDS clock, with jitter typically under 150 ps peak-to-peak. For 1080p at 60Hz, it uses 4 MIPI lanes with a pixel clock of 148.5 MHz, and each lane runs at 742.5 Mbps. The chip’s package is a 9x9mm BGA with 0.8mm pitch, which makes it suitable for compact adapter boards.
The Analog Devices ADV7535 is another popular chipset, but it’s designed for higher-end applications. It supports HDMI 1.4b input up to 4K at 30Hz and MIPI DSI output with up to 4 lanes at 1.5 Gbps per lane, giving a total bandwidth of 6 Gbps. However, the ADV7535 requires an external DDR3 memory (typically 128 MB to 512 MB) for frame buffering, because it uses a store-and-forward architecture to handle resolution mismatches and timing corrections. This adds cost and board area—around 50 mm² for the memory chip alone. The chip also includes an integrated audio codec for I2S output, and it supports HDCP 1.4 and 2.2. Its power consumption is higher, around 800 mW to 1.2 W, due to the memory interface. The ADV7535 is often used in automotive and industrial displays where reliability and timing accuracy are critical, but it’s overkill for simple 1080p adapters.
Lattice Semiconductor’s CrossLink FPGAs, such as the LIF-MD6000, offer a programmable alternative. These FPGAs have up to 6.2 K logic cells and 128 Kbit of block RAM, and they support MIPI D-PHY at up to 1.5 Gbps per lane. You can program them to implement custom video processing, like color space conversion (RGB to YUV), gamma correction, or frame rate conversion. For example, you can use a CrossLink to convert 4K at 60Hz HDMI input to 1080p at 60Hz MIPI DSI output by downscaling in real-time, which dedicated chips can’t do. However, FPGAs require external configuration memory (SPI flash), power sequencing, and careful PCB layout for high-speed signals. Their power consumption is typically 1.5 W to 3 W, and the BOM cost is higher—around $15 to $25 for the FPGA plus $5 for configuration memory, compared to $8 to $12 for the TC358870XBG. FPGAs are used in prototyping and low-volume production where flexibility is more important than cost.
MIPI DSI Lane Configuration and Bandwidth Calculations
The number of MIPI DSI lanes directly determines the maximum resolution and refresh rate an adapter can support. For a given resolution, the required MIPI bandwidth is calculated as: (horizontal pixels + horizontal blanking) x (vertical pixels + vertical blanking) x bits per pixel x refresh rate. For 1920x1080 at 60Hz with 24-bit color, typical blanking totals 2800 horizontal and 1125 vertical, giving 2800 x 1125 x 24 x 60 = 4.536 Gbps. With 4 MIPI lanes at 1 Gbps each, the total bandwidth is 4 Gbps, which is insufficient—so adapters use reduced blanking (CVT-RB) timings, like 2200 horizontal and 1125 vertical, giving 2200 x 1125 x 24 x 60 = 3.564 Gbps, which fits within 4 Gbps. For 4K at 30Hz, the required bandwidth is 3840 x 2160 x 24 x 30 = 5.97 Gbps (with standard blanking), exceeding 4 Gbps, so adapters use 4 lanes at 1.5 Gbps (6 Gbps total) or reduce color depth to 18-bit. The TC358870XBG supports only 1 Gbps per lane, so it can’t do 4K at 30Hz with full 24-bit color—it requires 18-bit or reduced blanking. The ADV7535 with 1.5 Gbps lanes can handle 4K at 30Hz with 24-bit color, but only if the HDMI input uses reduced blanking timings.
EDID Emulation and HDCP Handling
All three chipsets include EDID (Extended Display Identification Data) emulation, which tells the HDMI source what resolution and timing the MIPI panel supports. The TC358870XBG has an internal 128-byte EEPROM that stores a default EDID, but you can reprogram it via I2C to match your panel’s exact timings. For example, a 5-inch 800x480 panel would require an EDID with 800x480 at 60Hz, with a pixel clock of 33.26 MHz. The ADV7535 has a more advanced EDID manager that can handle multiple timing blocks and support 4K resolutions. HDCP (High-bandwidth Digital Content Protection) is handled differently: the TC358870XBG supports HDCP 1.4 only, so it can’t decrypt 4K content from Blu-ray players or streaming devices that use HDCP 2.2. The ADV7535 supports both HDCP 1.4 and 2.2, making it suitable for protected content. The Lattice FPGA can implement HDCP decryption in soft IP, but this requires a license from Digital Content Protection LLC, costing around $10,000 per year for commercial use.
Power Supply and PCB Design Considerations
These chipsets require multiple voltage rails: 1.2V for core logic, 1.8V for I/O, and 3.3V for HDMI and MIPI termination. The TC358870XBG consumes 300 mW to 500 mW, so a linear regulator like the AMS1117-3.3 is sufficient. The ADV7535 with external memory draws 800 mW to 1.2 W, requiring a switching regulator for efficiency. The Lattice FPGA needs 1.1V core, 1.8V I/O, and 2.5V for PLLs, with total power up to 3 W. PCB layout is critical: MIPI DSI traces must be impedance-matched to 50 ohms single-ended or 100 ohms differential, with length matching within 0.5 mm for each lane. HDMI traces require 100-ohm differential impedance and must be shorter than 150 mm to avoid signal degradation. The TC358870XBG’s BGA package requires 4-layer PCBs at minimum, while the ADV7535 and FPGA often need 6-layer boards for signal integrity.
Real-World Performance Benchmarks
In practical tests, the TC358870XBG achieves 1080p at 60Hz with 24-bit color on a 7-inch MIPI DSI panel (1024x600) without any frame drops. Latency is measured at 1.5 to 2.5 ms from HDMI input to MIPI output, which is acceptable for real-time video. For 4K at 30Hz, the same chip shows occasional tearing if the HDMI source uses non-standard timings, because the chip lacks a frame buffer. The ADV7535 with 128 MB DDR3 memory handles 4K at 30Hz smoothly, with latency under 5 ms. The Lattice FPGA can achieve 1080p at 60Hz with custom gamma correction and color space conversion, but latency increases to 8-12 ms due to the frame buffer. Thermal performance: the TC358870XBG operates at 40°C to 85°C ambient, while the ADV7535 runs 10°C hotter due to the memory interface. The FPGA can get up to 70°C without a heatsink, requiring forced air cooling in enclosed enclosures.
Compatibility with MIPI DSI Panels
MIPI DSI panels come in two types: command mode (using DCS commands) and video mode (continuous streaming). The TC358870XBG supports both, but it’s optimized for video mode, which is used by most consumer displays. Command mode requires additional initialization sequences, which the chip can handle via its I2C interface. For example, a 3.5-inch 480x320 panel might need a specific DCS command to set the sleep-out and display-on registers. The ADV7535 has a built-in panel sequencer that automatically sends these commands based on a lookup table. The Lattice FPGA requires you to implement the panel initialization in Verilog or VHDL, which is more complex but allows custom sequences for exotic panels. Voltage levels: MIPI DSI uses 1.2V logic, while HDMI uses 3.3V. All three chipsets have level shifters built in, but you must ensure the MIPI DSI connector’s pinout matches your panel—common pinouts include 30-pin, 40-pin, and 50-pin FPC connectors with 0.5mm or 1.0mm pitch.
Cost and Availability
As of 2025, the TC358870XBG costs $8 to $12 in single quantities from distributors like Digi-Key or Mouser, with lead times of 4 to 6 weeks. The ADV7535 is $15 to $20, plus $3 to $5 for the external DDR3 memory. The Lattice LIF-MD6000 is $15 to $25, plus $2 for configuration flash and $5 for a programming cable. For a complete adapter board, the BOM cost ranges from $25 to $40 for the TC358870XBG design, $40 to $60 for the ADV7535, and $50 to $80 for the FPGA design. The DisplayModule adapter uses the TC358870XBG because it balances cost and performance for most embedded applications, supporting resolutions up to 1920x1080 at 60Hz and 3840x2160 at 30Hz with reduced color depth.
Alternative Chipsets and Emerging Trends
Other chipsets include the ITE IT66121, which is a low-cost HDMI to MIPI DSI bridge for 1080p at 60Hz, costing $5 to $8. It supports 4 MIPI lanes at 1 Gbps but lacks HDCP and audio support. The Parade Technologies PS8625 is another option, used in some display adapters, but it’s being phased out due to limited availability. Emerging chipsets from companies like Novatek and Realtek are integrating HDMI to MIPI DSI conversion with TCON (timing controller) functionality, reducing the need for separate chips. For example, the Novatek NT98520 combines an HDMI receiver, MIPI DSI transmitter, and TCON for panels up to 4K at 60Hz, but it’s only available in high volume (10,000+ units). For now, the TC358870XBG remains the most widely used chipset in HDMI to MIPI DSI adapters, including the DisplayModule board, due to its proven reliability, low power, and reasonable cost. If you need 4K at 60Hz or HDCP 2.2, consider the ADV7535 or an FPGA-based design, but expect higher cost and complexity.